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Agilent HDMP-1687 Four Channel SerDes Circuit for Gigabit Ethernet and Fibre Channel
Data Sheet
Features * Four ANSI x3.230- 1994 Fibre Channel (FC-O) or IEEE 802.3z Gigabit Ethernet compatible SerDes in a single package * Supports serial data rates of 1062.5 MBd (Fibre Channel) & 1250 MBd (Gigabit Ethernet) * Based on X3T11 Fibre Channel "10 bit specification" * Uses reference clock (RFCT) for Tx data latching * Half or full speed Rx clocks * 5-Volt tolerant TTL I/Os * Low power consumption * 208 ball, 23 mm TBGA package * Single +3.3 V power supply * 1.5 kV ESD protection on all pins * Equalizers on inputs * Copper drive capability * Buffered line logic outputs Applications * 1250 MBd Gigabit Ethernet high density ports * 1062.5 MBd Fibre Channel interface * Mass storage system I/O channel * Work station/server I/O channel * FC interface for disk drives and arrays * Serial backplanes * Clusters per the 8B/10B encoding scheme, with special reserve characters for link management purposes. Other encoding schemes will also work as long as they provide dc balance and sufficient transition density. In order to accomplish this task, the SERDES circuitry incorporates the following:
Functional Description The HDMP-1687 is a four channel SERDES device. HDMP-1687 is in a 208-ball TBGA package with four 1.0625/1.25 Gbps serial I/O. This integrated circuit provides a lowcost, low-power, small-form-factor physical-layer solution for multi-link Gigabit Ethernet/Fibre Channel interfaces. This IC may be used to directly drive copper cables, or it may be used to interface with optical transceivers. Each IC contains transmit and receive channel circuitry for all four channels. The transmitter section accepts 10-bit-wide parallel TTL data on each channel and serializes it into a high-speed serial stream. The parallel data is expected to be 8B/10B encoded (or equivalent). Four banks of parallel data are latched into the input registers of the transmitter sections on the rising edge of RFCT. Receive data are latched out with separate clock pins for each channel. These pins may be single 106.25/125 MHz TTL clock outputs RC [0:3] [1] or dual 53.125/62.5 MHz TTL pairs RC [0:3] [0:1] to serve legacy applications where
single SerDes devices were used before. The receive clock mode select (RCM0) pin is used to define the designer's choice. RCM0 Receive Clock Mode 0 half speed dual clocks 1 full speed single clocks The SYNC pin enables bytesync detection on all four channels. When a comma character is detected on any channel, its corresponding SYN [0:3] pin goes high. A single LOOP pin is provided for all channels to enable the local loopback function. HDMP-1687 Block Diagram The following is a description of the blocks in each channel. Except for the transmit PLL section, circuits for the channels are independent. Figure 1 shows how this IC may be connected to a protocol device that controls four channels. Each channel of the four channel SERDES (Figure 2) was designed to transmit and receive 10-bitwide characters over dedicated differential high-speed lines. The parallel data applied to the transmitter is expected to be encoded
* * * *
TTL parallel I/Os High-speed phase locked loops Parallel-to-serial converter High-speed serial clock and data recovery circuitry * Comma character recognition circuitry for 8B/10B * Character alignment circuitry * Serial-to-parallel converter PARALLEL INPUT LATCH The transmitter accepts 10-bit wide single-ended TTL parallel data at inputs TX [0:3] [0:9]. The RFCT pin is used as transmit byte clock. The TX [0:3] [0:9] and RFCT signals must be properly aligned, as shown in Figure 3. RFCT is also used as a clean frequency reference for the receiver PLLs. TX PLL/CLOCK GENERATOR The transmitter Phase Locked Loop and Clock Generator (TX PLL/CLOCK GENERATOR) block generates all internal clocks needed by the transmitter section to perform its functions. These clocks are based on the supplied reference clock (RFCT). RFCT is used as the frequency reference clock for the PLL as well as for the incoming data latches. The RFCT clock is multiplied by 10 to generate the serial rate clock necessary for clocking the high speed serial outputs. FRAME MUX The FRAME MUX accepts the 10-bit wide parallel data from the INPUT LATCH. Using internally generated high speed clocks, this parallel data is multiplexed into serial data streams. The data bits are transmitted sequentially, from TX [0:3] [0] to TX [0:3] [9]. SERIAL OUTPUT SELECT The OUTPUT SELECT block provides for an optional internal loopback of the high speed serial signal for testing purposes. 2
In normal operation, LOOP is set low and the serial data stream is placed at SO [0:3] . When wrap-mode is activated by setting LOOP high, the SO [0:3] pins are held static at logic 1 and the serial output signal is internally wrapped to the INPUT SELECT block of the receiver section. SERIAL INPUT SELECT The INPUT SELECT block determines whether the signal at SI [0:3] or the internal loopback serial signal is used. In normal operation, LOOP is set low and the serial data is accepted at SI [0:3] . When LOOP is set high, the outgoing high speed serial signal is internally looped-back from the transmitter section to the receiver section. This feature allows parallel loopback testing, exclusive of the transmission medium. RX PLL/CLOCK RECOVERY The RX PLL/CLOCK RECOVERY block is responsible for frequency and phase locking onto the incoming serial data stream and recovering the bit and byte clocks. The Rx PLL continually frequency locks onto the reference clock, and then phase locks onto the selected input data stream. The frequency lock part of the PLL is shared among all channels. Phase locking is performed separately on each channel. An internal signal detection circuit monitors the presence of the input, and invokes the phase detection once the minimum differential input signal level is supplied (AC Electrical Specifications). Once bit locked, the receiver generates the high speed sampling clock at serial data rates for the input sampler. SERIAL INPUT SAMPLER The INPUT SAMPLER converts the serial input signal into a high speed serial bit stream. In order
to accomplish this, it uses the high speed serial clock recovered from the RX PLL/CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX AND BYTE SYNC block. FRAME DEMUX, BYTE SYNC The FRAME DEMUX, BYTE SYNC block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. This block is also responsible for recognizing the comma character (K28.5+) of positive disparity (0011111xxx). When recognized, the FRAME DEMUX, CHAR SYNC block works with the RX PLL/CLOCK RECOVERY block to properly select the parallel data edge out of the bit stream so that the comma character starts at bit RX [0:3] [0]. When a comma character is detected and realignment of the receiver byte clock RC [0:3] [0:1] is necessary, this clock is stretched, not slivered, to the next possible correct alignment position. This clock will be fully aligned by the start of the second 4-byte ordered set. The second comma character received will be aligned with the rising edge of RC [0:3] [1] and will follow it with a delay. This delay guarantees hold time at the receiving ICs input latches. Comma characters of positive disparity must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. PARALLEL OUTPUT DRIVERS The OUTPUT DRIVERS present the 10-bit parallel recovered data byte properly aligned to the receive byte clocks RC [0:3] [0:1] as shown in Figure 5. These output data buffers provide single ended TTL compatible signals.
RFCT
4-CHANNEL MAC
RC0
RC1
RC2
RC3
RX0
RX1
RX2
RX3
TX0
TX1
TX2
HDMP-1687
SO0
SO1
SO2
SO3
SI0
SI1
SI2
Figure 1. Typical application using HDMP-1687.
INPUT LATCH
TX[0:3][0:9]
FRAME MUX
SI3
TX3
OUTPUT SELECT
SO [0:3]
LOOPBACK CAP0 CAP1 TX PLL CLOCK GENERATOR TX CLOCKS INPUT SELECT
LOOP
SI [0:3]
RFCT RX PLL CLOCK RECOVERY
RC[0:3][0] RC[0:3][1]
OUTPUT DRIVER
RX [0:3][0:9]
FRAME DEMUX AND BYTE SYNC
RX CLOCKS
INPUT SAMPLER
SYN [0:3] SYNC
Figure 2. Block diagram of HDMP-1687.
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Timing Characteristics for Gigabit Ethernet - Transmitter Section T = 0C Ambient to +85C Case, VCC = 3.15 V to 3.45 V Symbol Ttxsetup Ttxhold t_txlat[1] Parameter Tx Input Setup Time Tx Input Hold Time Transmitter Latency Units ns ns ns bits Min. 1.5 0.5 2.3 2.8 Typ. Max.
Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
Timing Characteristics for Fibre Channel - Transmitter Section T = 0C Ambient to +85C Case, VCC = 3.15 V to 3.45 V Symbol Ttxsetup Ttxhold t_txlat[1] Parameter Tx Input Setup Time Tx Input Hold Time Transmitter Latency Units ns ns ns bits Min. 2.0 1.5 3.8 4.0 Typ. Max.
Note: 1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, RFCT) and the transmission of the first serial bit of that parallel word (defined by the edge of the first bit transmitted).
RFCT
1.4 V
2.0 V TX [0:3] [0:9] DATA DATA DATA DATA DATA 0.8 V ttxsetup ttxhold
Figure 3. Transmitter section timing.
TX BYTE A
TX BYTE B
SO [0:3]
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
S6
t_txlat
TX [0:3] [0:9]
TX BYTE B
TX BYTE C
RFCT
Figure 4. Transmitter latency.
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Timing Characteristics for Gigabit Ethernet - Receiver Section T = 0C Ambient to +85C Case, VCC = 3.15 V to 3.45 V Symbol Parameter f_lock Frequency Lock at Powerup b_sync [1,2] Bit Sync Time trxsetup RX [0:3][0:9] Output Setup Time (Data Valid Before Clock) trxhold RX [0:3][0:9] Output Hold Time (Data Valid After Clock) Tduty RC [0:3][0] and RC [0:3][1] Duty Cycle tA-B Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) [3] t_rxlat Receiver Latency
Units s bits ns ns % ns ns bits
Min.
Typ.
Max. 500 2500
2.5 2.0 40 7.5 20.7 26.0
60 8.5
Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using C PLL = 0.1 F. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
Timing Characteristics for Fibre Channel - Receiver Section T = 0C Ambient to +85C Case, VCC = 3.15 V to 3.45 V Symbol Parameter f_lock Frequency Lock at Powerup b_sync [1,2] Bit Sync Time trxsetup RX [0:3][0:9] Output Setup Time (Data Valid Before Clock) trxhold RX [0:3][0:9] Output Hold Time (Data Valid After Clock) Tduty RC [0:3][0] and RC [0:3][1] Duty Cycle tA-B Rising Edge Time Difference between RBC0 and RBC1 (Half Rate) [3] t_rxlat Receiver Latency
Units s bits ns ns % ns ns bits
Min.
Typ.
Max. 500 2500
3.0 1.5 40 8.9 22.4 28.0
60 9.9
Notes: 1. This is the recovery time for input phase jumps, per the Fibre Channel Specification X3.230-1994 FC-PH Standard, Sec 5.3. 2. Tested using C PLL = 0.1 F. 3. The receiver latency, as shown in Figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, RC[0:1]).
trxsetup trxhold
RC [0:3] [1]
1.4 V
2.0 V RX [0:3] [0:9] K28.5+ DATA DATA DATA DATA 0.8 V 2.0 V SYNC 0.8 V
RC [0:3] [0]
1.4 V
Figure 5a. Receiver section timing (dual receive clocks).
tA-B
5
trxsetup trxhold
RC [0:3] [1]
1.4 V
2.0 V RX [0:3] [0:9] K28.5 DATA DATA DATA DATA 0.8 V
Figure 5b. Receiver section timing (single receive clock).
RX BYTE A
RX BYTE B
SI [0:3]
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S0
S1
S2
S3
S4
S5
S6
t_rxlat
RX [0:3] [0:9]
RX BYTE A
RC [0:3] [1]
Figure 6. Receiver latency.
Absolute Maximum Ratings TA = 25C, except as specified. Operation in excess of any one of these conditions may result in permanent damage to this device. Continuous operation at these minimum or maximum ratings is not recommended. Symbol VCC VIN,TTL VIN,HS_IN IO,TTL Tstg Tj TC Parameter Supply Voltage TTL Input Voltage HS_IN Input Voltage (Differential) TTL Output Sink / Source Current Storage Temperature Junction Temperature Case Temperature Units V V V mA C C C -65 0 0 Min. -0.5 -0.7 Max. 4.0 VCC + 2.8 2.2 13 +150 +125 +95
Guaranteed Operating Rates T = 0C Ambient to +85C Case, VCC = 3.15 V to 3.45 V Parallel Clock Rate (MHz) Min. Max. 124.0 105.25 6 126.0 107.25 Serial Baud Rate (MBaud) Min. Max. 1240 1052.5 1260 1072.5 Gigabit Ethernet Fibre Channel
Transceiver Reference Clock Requirements T = 0C Ambient to +85C Case, VCC = 3.15 V to 3.45 V Symbol f f Ftol Symm Parameter Nominal Frequency (for Gigabit Ethernet Compliance) Nominal Frequency (for Fibre Channel Compliance) Frequency Tolerance Symmetry (Duty Cycle) Units MHz MHz ppm % -100 40 Min. Typ. 125 106.25 +100 60 Max.
TTL I/O DC Electrical Specifications TA = 0C Ambient to +85C Case, V CC = 3.15 V to 3.45 V Symbol VIH,TTL VIL,TTL VOH,TTL VOL,TTL IIH,TTL IIL,TTL ICC,TRx Parameter TTL Input High Voltage Level, Guaranteed High Signal for All Inputs TTL Input Low Voltage Level, Guaranteed Low Signal for All Inputs TTL Output High Voltage Level, IOH = -400 A TTL Output Low Voltage Level, IOL = 1 mA Input High Current, VIN = 2.4 V, VCC = 3.45 V Input Low Current, VIN = 0.4 V, V CC = 3.45 V Transceiver V CC Supply Current, T A = 25C Units V V V V A A mA 800 Min. 2 0 2.2 0 Typ. Max. 5.5 0.8 VCC 0.5 40 -600
AC Electrical Specifications (TRx) TA = 0C Ambient to +85C Case, V CC = 3.15 V to 3.45 V Symbol tr,TCi tf,TCi tr,TTLin tf,TTLin tr,TTLout tf,TTLout trs, HS_OUT tfs, HS_OUT trd, HS_OUT tfd, HS_OUT VIP,HS_IN VOP,HS_OUT [1] Parameter RFCT Rise Time, 0.8 to 2.0 Volts RFCT Fall Time, 2.0 to 0.8 Volts Input TTL Rise Time, 0.8 to 2.0 Volts Input TTL Fall Time, 2.0 to 0.8 Volts Output TTL Rise Time, 0.8 to 2.0 Volts, 10 pF Load Output TTL Fall Time, 2.0 to 0.8 Volts, 10 pF Load HS_OUT Single-Ended SO [0:3] Rise Time HS_OUT Single-Ended SO [0:3] Fall Time HS_OUT Differential Rise Time HS_OUT Differential Fall Time HS_IN Input Peak-To-Peak Differential Voltage Units ns ns ns ns ns ns ps ps ps ps mV 200 1000 Min. 0.2 0.2 1.0 1.0 1.5 1.1 200 200 200 200 1200 1300 2.4 2.4 300 300 300 300 2000 1800 Typ. Max. 2.4 2.4
HS_OUT Output Pk-Pk Diff. Voltage (Z0=50 Ohms, Fig.10) mV
Note: 1. Output Peak-to-Peak Differential Voltage specified as SO [0:3]+ minus SO [0:3]-. The output will be 25% higher when terminating into 75 loads.
7
Figure 7a. Eye diagram of a high speed differential output for Gigabit Ethernet.
Figure 7b. Eye diagram of a high speed differential output for Fibre Channel.
Output Jitter Characteristics - Transmitter Section TA = 0C Ambient to +85C Case, V CC = 3.15 V to 3.45 V Symbol RJ[1] DJ[1] Parameter Random Jitter at SO [0:3], the High Speed Electrical Data Port, specified as 1 sigma deviation of the 50% crossing point (RMS) Deterministic Jitter at SO [0:3], the High Speed Electrical Data Port (pk-pk) Units ps ps Typ. 11 36
Note: 1. Defined by Fibre Channel Specification X3.230-1994 FC-PH Standard, Annex A, Section A.4 and tested using measurement method shown in Figure 8.
8
A 70311A CLOCK SOURCE
A 70841B PATTERN GENERATOR +K28.5, -K28.5
A 70841B PATTERN GENERATOR* 0000011111 + DATA - DATA 1.25 GHz A 70311A CLOCK SOURCE VARIABLE DELAY
A 83480A OSCILLOSCOPE TRIGGER 125 MHz CH1 CH2
DIVIDE BY 10 CIRCUIT (DUAL OUTPUT)
1.25 GHz
+ DATA - DATA A 83480A OSCILLOSCOPE
DIVIDE BY 2
TRIGGER CH1 CH2
+SOi BIAS TEE
-SOi
VARIABLE DELAY +SOi -SOi -SIi +SIi SYNC LOOP RXi(0..9)
HDMP-1687
RFCT LOOP
HDMP-1687
TTL 125 MHz RFCT TXi(0..9)
TXi(0-9) *PATTERN GENERATOR PROVIDES A DIVIDE BY 10 FUNCTION
1.4 V
0011111000 (STATIC K28.7)
B. BLOCK DIAGRAM OF DJ MEASUREMENT METHOD
A. BLOCK DIAGRAM OF RJ MEASUREMENT METHOD
Figure 8. Transmitter jitter measurement method.
Thermal and Power Characteristics (TRx) T = 0C Ambient to 85C Case, VCC = 3.15 V to 3.45 V Symbol PD, TRx JA[1] JC[2] JT[3] Parameter Transceiver Power Dissipation, Outputs Connected per Recommended Bias Terminations with Idle Pattern Thermal Resistance: Junction to Ambient Thermal Resistance: Junction to Case Thermal Characterization Parameter: Junction to Package Top Units W C/W C/W C/W Typ. 2.6 15.8 2.5 1.1 Max. 3.3
Notes: 1. JA is measured in a still air environment at 25C on a standard 3 x 3" FR4 PCB as specified in EIA/JESD 51-7. 2. JC data relevant for packages used with external heat sink. 3. To determine the actual junction temperature in a given application, use the following: TJ = TT + (JT x PD), where T T is the case temperature measured on the top center of the package and PD is the power being dissipated.
I/O Type Definitions I/O Type I-TTL O-TTL HS_OUT HS_IN C S Definition Input TTL, floats high when left open Output TTL 50 matched output driver. Will drive AC coupled 50 loads. PECL Level Compatible (Figure 10). PECL Level Compatible. Must be AC coupled (Figure 10). External Circuit Node Power Supply or Ground
Pin Input Capacitance (TRx) Symbol CINPUT 9 Parameter Input Capacitance on TTL Input Pins Units pF Typ. 1.6 Max.
O_TTL
VCC
I_TTL
VCC
VCC
VBB 1.4 V
GND GND ESD PROTECTION ESD PROTECTION GND
Figure 9. O-TTL and I-TTL simplified circuit schematic.
HS_OUT
VCC VCP Zo Zo VCC VCC
HS_IN
+ - VCC
+ -
SO[0:3]+ 0.01 F
Zo = 50
SI[0:3]+
2 * Zo = 100 SO[0:3]- 0.01 F GND ESD
PROTECTION
Zo = 50 SI[0:3]- GND *ESD
PROTECTION
GND
GND
NOTES: 1. HS_IN INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. 2. CAPACITORS MAY BE PLACED AT THE SENDING END OR THE RECEIVING END.
Figure 10. HS_OUT and HS_IN simplified circuit schematic.
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01 A B C D E F G H J K L M N P R T U GND
02 VCC
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
GND SYN1 RC10 RX10 RX14 RX16 VCR1 VCC
GND RX21 VCR2 RX28 GND VCR2 GND
RX07 RX08 RX09 GND RC11 RX11 VCR1 RX17 GND SYN2 RX20 RX22 RX25 RX29 SYN3 RC30 RC31 RX04 RX05 RX06 VCR0 VCR1 RX12 GND RX18 N/C RC20 VCR2 RX23 RX26 VCC VCR3 GND RX30 RX00 RX01 VCR0 GND GND RX13 RX15 RX19 N/C RC21 GND RX24 RX27 RX31 RX32 RX33 RX34 RC00 RC01 RX02 RX03 N/C SYN0 VCR0 GND TX18 TX19 GND VCC GND GNDA VCRX VCC VCCA VCPX VCR3 GND RX35 RX36 RX37 RX38 RX39 GND TX22 TX21 TX20 VCR3 TX26 TX25 TX24 TX23 VCC TX29 TX28 TX27 GND GND VCC N/C
TX14 TX15 TX16 TX17 TX10 TX11 TX12 TX13 N/C N/C GND GND VCC
TX08 TX09 GND
TX33 TX32 TX31 TX30 TX37 TX36 TX35 TX34 LOOP VCC TX39 TX38 N/C GND N/C N/C
TX04 TX05 TX06 TX07 TX00 TX01 TX02 TX03 N/C N/C N/C GND VCC
GND SO0- GND SO1- GND CAP0 GND SO2+ GND SO3+ GND VCC SO0+ GND SO1+ GNDA CAP1 GND SO2- GND SO3- VCC VCC VCP0 GND VCP1 GND VCCA GND VCP2 GND VCP3 VCC SI1- SI1+ GND GND SI2- SI2+ GND SI3-
RFCT N/C RCM0* GND
VCC SYNC N/C
GND GND
GND GND SIO- SIO+ VCC
SI3+ GND GND GND
* Previously RFC1 changed to RFCT for data sheet consistency. Figure 11. Pinout of HDMP-1687 (top view).
Filtering Schematic
01 0.1 F A B C D E F G H J VCR GND GND VCC * 10 F PLACEMENT NOT CRITICAL - INDICATES NEED FOR LOW-FREQUENCY BYPASS CAPACITANCE VCC VCR GND VCC GND GND VCR GND VCR GND 0.1 F VCR GND 02 03 04 05 06 07 08 09 10 10 F* VCR GND VCR GND VCR GND GND VCR VCC VCR GND VCC GND VCR 11 12 13 14 15 0.1 F GND VCR GND 16 17
0.1 F
0.1 F 0.1 F
0.1 F
K L M N P R T U GND GND GND
GND GND
GND VCC 0.1 F GND GND GND VCP VCC 0.1 F GND VCP GND GND GND GND VCP GND GND GND GND 0.1 F
GND
GND
HDMP-1687
VCC
VCC
0.1 F
GND VCC VCP VCC GND GND GND VCC GND GND GND
GND VCC
VCC VCC
GND VCCA GND GND GND 0.1 F 10 F
0.1 F
TO VCCA PI-FILTER (SEE SCHEMATIC)
11
Guidelines for Decoupling Capacitor Placements/Connections
+ 10 F *
VCC
A10
A13
VCC
A2
VCR VCC
VCR
VCR VCR
A16
B7
A9
0.1 F
0.1 F
0.1 F
C4 0.1 F C5 D3 F3 G4
VCR VCR VCR VCR VCC
VCR VCC VCR VCR
C11 C14 C15 E14 G17 J14 K16
0.1 F
L4 0.1 F
HDMP-1687 GUIDELINES FOR DECOUPLING CAPACITOR PLACEMENTS/CONNECTIONS
VCR VCC VCC
0.1 F
VCC VCC N15
0.1 F
0.1 F R4 VCC VCC R16
VCCA
VCP VCC
VCP
VCP
VCP T13
VCC VCC
VCC T14
T11
T3 T4
T5
U5
T7
T9
0.1 F
0.1 F
VCC 0.1 F +
1 H 10 F 10 F + + 0.1 F
* PLACEMENT NOT CRITICAL.
INDICATES THE NEED FOR ADDITIONAL LOW FREQUENCY CAPACITIVE DECOUPLING.
+ OPTIONAL - PROVIDES INCREASED LOW FREQUENCY DECOUPLING.
12
R14
0.1 F
VCC
TRx I/O Definition Name SI [0:3]+ SI [0:3]- SO [0:3]+ SO [0:3]- SYNC Type HS_IN HS_ OUT I-TTL Signal Serial Data Inputs: High-speed inputs. Serial data is accepted from the SI [0:3] inputs when LOOP is low. Serial Data Outputs: High speed outputs. These lines are active when LOOP is set low. When LOOP is set high, these outputs are held static at logic 1. Enable Byte Sync Input: When high, turns on the internal byte sync functions to allow clock synchronization to a comma character of positive disparity (0011111XXX). When the line is low, the function is disabled and will not reset registers and clocks, or strobe the SYN [0:3] lines. Byte Sync Outputs: Active high outputs. Used to indicate detection of a comma character of positive disparity (0011111XXX) when SYNC is enabled. These pins need to be left open. Do not apply voltage on this pin. I-TTL Loopback Enable Input: When set high, the high speed serial signal is internally wrapped from the transmitter's serial loopback outputs back to the receiver`s loopback inputs. Also when in loopback mode, the SO [0:3] outputs are held static at logic 1. When set low, SO [0:3] outputs and SI [0:3] inputs are active. Receivers Clocking Mode Definition Pins: These pins define how received parallel data are driven as follows: RCM0 Receive Clock Mode 0 half speed dual clocks 1 full speed single clocks Receiver Byte Clocks: The receiver sections drive 125 MHz receive byte clocks RC [0:3] [1]. Alternatively, they may drive half speed clocks RC [0:3] [0:1]. See RCM0 definition. Reference Clock and Transmit Byte Clock: A 125 MHz clock supplied by the host system. The transmitter sections accept this signal as the frequency reference clock. It is multiplied by 10 to generate the serial bit clock and other internal clocks. The transmit sections use this clock as the transmit byte clock for transmitting parallel data at TX [0:3] [0:9]. Data Outputs: Four 10 bit data bytes. RX [0:3] [0] are the first bits received.
SYN [0:3] N/C LOOP
O-TTL
RCM0
I-TTL
RC [0:3] [0:1]
O-TTL
RFCT
I-TTL
RX [0:3] [0] RX [0:3] [1] RX [0:3] [2] RX [0:3] [3] RX [0:3] [4] RX [0:3] [5] RX [0:3] [6] RX [0:3] [7] RX [0:3] [8] RX [0:3] [9] CAP0 CAP1
O-TTL
C
Loop Filter Capacitor: A loop filter capacitor for the internal PLLs must be connected across the CAP0 and CAP1 pins. (typical value = 0.1F).
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TRx I/O Definition, continued Name TX [0:3] [0] TX [0:3] [1] TX [0:3] [2] TX [0:3] [3] TX [0:3] [4] TX [0:3] [5] TX [0:3] [6] TX [0:3] [7] TX [0:3] [8] TX [0:3] [9] VCC VCCA VCR3-0 VCP3-0 Type I-TTL Signal Data Inputs: Four 10 bit, 8B/10B encoded data bytes. TX [0:3] [0] are the first bits transmitted.
S S S S
Power Supply: Nominally 3.3 volts. Used for logic and TTL inputs. Analog Power Supply: Nominally 3.3 volts. Used to provide a clean supply line for the PLLs and high speed analog cells. Rx TTL Output Power Supply: Nominally 3.3 volts. Used for all TTL receiver output buffer cells. High Speed Output Supply: Nominally 3.3 volts. Used only for the last stage of the high speed transmitter output cells (HS_OUT) as shown in Figure 10. Due to high current transitions, this Vcc should be well bypassed to a ground plane. Ground: Nominally 0 volts. All GND pads on the chip are connected to one ground slug in the package which then distributes these to GND balls. Analog Ground: Normally 0 volts. All GND pads on the chip are connected to one ground slug in the package, which then distributes these to GND balls.
GND GNDA
S S
208 Ball 23 mm x 23 mm TBGA Package Drawing
A1 CORNER
HDMP-1687 ABCD-N RE.FG S YYWW HONG KONG
TOP VIEW Procedure to follow for soldering the HDMP-1687, 208-ball TBGA package: IR or Convective Reflow per IPC/JEDEC J-STD-020A standard for BGA IR Reflow.
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Package Drawing
D1 S e O (4x)
A2 A
e
S
E1
E D C B A 12345 Nx0b eee M Z X Y (CAVITY DOWN) (BACKFILL) DETAIL A ddd Z
[-Z-] SEATING PLANE
A1 CORNER [-Y-]
D
[-X-]
[-Z-] SEATING PLANE
A3
A1
(BACKFILL) DETAIL A E DIMENSIONS IN MILLIMETERS SYMBOL MIN. NOM. A A1 A2 A3 D D1 E E1 MD/ME N TOLERANCE OF FORM AND POSITION SYMBOL MIN. NOM. MAX. ddd eee 0.15 0.30 N1 O b e 0.60 0.60 0.75 1.27 0.10 0.90 1.35 0.60 0.85 0.15 23.00 0.20 20.32 BSC 23.00 0.20 20.32 BSC 17 208 4 1.50 0.65 0.90 MAX. 1.65 0.70 0.95
15
www.semiconductor.agilent.com Data subject to change. Copyright (c) 2001 Agilent Technologies, Inc. September 21, 2001 Obsoletes 5988-1305EN 5988-4080EN

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